Improving the efficiency of multiprocessor system through in-line interface network aggregation

Abstract

This paper outlines ways to increase the efficiency of a multiprocessor system by changing the architecture of its network interface. It is established that the undoubted advantage of channels aggregation mode is a significant increase of data interchange between computing nodes of a multiprocessor system and a significant decrease in deceleration rate. The analytical ratios for the computations deceleration coefficient are derived. There was executed the stage of computations deceleration factor simulation and the regularity of its change depending on the applied computing platforms executed. It is shown that due to the mode of network interface channels aggregation, the multiprocessor system operation reliability increases. The current operating mode of the multiprocessor system network interface provides greater possibilities for implementation of data interchange procedure between the computing nodes, significantly improving the characteristics of its efficiency, performance and reliability of its operation.