Chaotic oscillations in RLD circuits

Abstract

The aim of the work is to develop a mathematical model of the RLD circuit and to study the influence of the frequency w and amplitude U of the input harmonic voltage on the maximum value of voltage Ud  on the semiconductor diode. To solve this problem, we used the Multisim modeling environment.
If the barrier capacitance of the diode dominates due to the choice of the corresponding operating point, such an RLD circuit is described by non-linear differential equation of Duffing class.
In the first step studies but the effect of the amplitude U when it is an increase and decrease in the input signal max(Ud ). A sequential increase and then a decrease in the amplitude U of harmonic oscillations showed the presence of a hysteresis loop in the range of U values. This interval is characterized by the occurrence of chaotic oscillations.
In the second step studies but the influence of frequency w input harmonic voltage when it increases and decreases at max(Ud ). A sequential increase and then a decrease in the frequency w of harmonic oscillations at a constant amplitude U showed the presence of a hysteresis loop in the range of values of w. This interval is characterized by the occurrence of chaotic oscillations.
Thus, the occurrence of chaotic oscillations can be caused by both changes in the amplitude and frequency of the input harmonic signal.
Based on the computer model considered, it was possible to predict the bifurcation points of the hysteresis loop to determine the critical modes of real elements of electronic circuits.