HARDWARE IMPLEMENTATION DESIGN OF A SPIKING NEURON
DOI:
https://doi.org/10.34185/1562-9945-1-132-2021-10Keywords:
neuromorphic chip, spiking neuron network, neuron, synapse, weight coefficients, EDA, VLSIAbstract
The hardware implementation of an artificial neuron is the key problem of the design of neuromorphic chips which are new promising architectural solutions for massively parallel computing. In this paper an analog neuron circuit design is presented to be used as a building element of spiking neuron networks. The design of the neuron is performed at the transistor level based on Leaky Integrate-and-Fire neuron implementation model. The neuron is simulated using EDA tool to verify the design. Signal waveforms at key nodes of the neuron are obtained and neuron functionality is demonstrated.
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